This application claims the priority of Korean Patent Application No. 2002-56236 filed on Sep. 16, 2002, in the Korean Intellectual Property Office, the contents of which are incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a dual rail bus driver, and more particularly, to a skew-free dual rail bus driver.
2. Description of the Related Art
In general, data, which is carried in a dual rail bus in which precharge and evaluation occur, passes through a decoder or a multiplexer logic and is then fetched by a clock. The fetched data is again transmitted to the dual rail bus. Dual signals input to the decoder or the multiplexer logic are decoded into a single signal, again converted into dual data, and transmitted to an internal dual rail bus. The precharge refers to a case where dual signals passing through the dual rail bus are both at high levels, and the evaluation refers to a case where the level of one of the dual signals changed to a low level because data is carried, as shown in FIG. 1(a) or (b). FIG. 1(a) shows the states of the dual rail bus in which the precharge and evaluation occur, and FIG. 1(b) shows the states of the dual rail bus together.
While the single signal is converted into the dual signals, skew may occur due to a structural difference in delay between the dual signals. After the internal dual rail bus consisting of the precharge and evaluation periods is precharged, a data bus in which data is carried is discharged by malfunctions caused by the skew. Accordingly, the internal dual rail bus may malfunction.
FIG. 2 is a circuit diagram of a conventional dual rail bus driver. FIGS. 3(a) and 3(b) show timing diagrams of signals output from the dual rail bus driver of FIG. 2. Hereinafter, the operation of the conventional dual rail bus driver will be described with reference to FIGS. 2, 3(a), and 3(b).
When two signals pass through a logic 200 and a first driver 210 according to a clock CLK, the two signals are output as dual signals of different levels as shown in the signal of nodes 1 and 2 of FIG. 3(a). The dual signals become a single signal while passing a decoder 220, as shown in the signal of node 3 of FIG. 3(a). Inverter delayers 230 and 240 use the single signal output from the decoder 220 to drive the dual rail bus. After the single signal passes through the inverter delayers 230 and 240, complementary signals, as shown as nodes 4 and 5 of FIG. 3(a), are generated from the inverter delayers 230 and 240. Since the inverter delayers 230 and 240 have different numbers of stages, the signal of node 5 is delayed more than the signal of node 4. In this case, signals of nodes 4 and 5 may be at high levels at the same time. The clock signal CLK input to a clock delayer 250 is sufficiently delayed and becomes a delayed clock CLK_d. If the clock CLK is delayed for more than a predetermined time, both of the complementary signals, which are input to a second driver 260 in response to the delayed clock CLK_D, reach high levels at nodes 6 and 7, i.e., skew occurs.
In contrast, if the clock CLK is insufficiently delayed by the clock delayer 250, signals at nodes 6 and 7 are at low levels as the nodes 6 and 7 shown in FIG. 3(b), thereby causing the occurrence of a xe2x80x9cfailxe2x80x9d state.
In order to prevent malfunctions of the dual rail bus driver caused by skew or the xe2x80x9cfailxe2x80x9d state, it is required to further include protective MOSs 260-1 and 260-2 in the conventional dual rail bus driver.
Therefore, skew-free dual rail bus driver is required to prevent discharging of data.
The present invention provides a dual rail bus driver in which changes in phases of dual signals output from a first driver are detected, the detection result is used as a clock, and an edge trigger flip-flop is triggered according to the clock, thereby generating skew-free dual signals input to a second driver without using inverter delayers adopted by a conventional dual rail bus driver.
According to an aspect of the present invention, there is provided a dual rail bus driver including a first driver outputting first dual signals of the same level, and outputting second dual signals of different levels when a level of a clock changes. A decoder receives the second dual signals and outputs a single signal. A dual signal controller is triggered due to a change in the level of the second dual signals and outputs third dual signals of different levels in response to the single signal at the same time. A second driver inverts the levels of the third dual signals output from the dual signal controller and outputs fourth dual signals in accordance with a change in the level of the clock.
In one embodiment, the dual signal controller includes a phase change detector detecting changes in the phases of the second dual signals and outputting the detection result as an edge signal and an edge trigger flip-flop being triggered by the edge signal and outputting the third dual signals in response to the single signal at the same time.
The edge trigger flip-flop can be a flip-flop of a sense amplifier type.
In one embodiment, the second driver is implemented without protective MOS devices.